Instruction pipeline
lastmod 2018-08-17created 2015-10-052 edits
An instruction pipeline is a technique applied to processors that read and execute instructions sequentially. Rather than executing only one instruction at a time, it executes several instructions simultaneously by starting the execution of another instruction while one instruction is still being executed.
A single instruction can be divided into several stages. If the next instruction waits without being processed until one instruction has finished, then while a particular stage of an instruction is being processed, the parts that handle the other stages sit idle. With a pipeline, while one part processes a particular stage of one instruction, other parts can process other stages of other instructions, so speed can improve.
Pipeline efficiency drops as branches and subroutine calls increase. This is because when a branch or subroutine call occurs, all the instructions being processed in the pipeline are canceled and the instructions of the branch or subroutine must be processed anew. Modern architectures avoid this problem through techniques such as branch prediction.
RISC processors have better pipeline efficiency than CISC processors. Because RISC instructions are processed in one clock, processing of the next instruction is not delayed by one instruction taking a long time. Also, memory access takes a very long processing time, and since RISC accesses memory only through LOAD or STORE instructions, there are fewer inefficient accesses than in CISC.