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Central processing unit

lastmod 2024-07-09created 2015-04-0422 edits

A central processing unit (中央處理裝置; North Korean standard term: jungang cheori soja) or CPU is the part of a computer where software instructions are executed, or a chip that has that function built in. The central processing unit (CPU) in a computer receives information from outside, stores it, interprets and computes the instructions of computer programs, and outputs results externally. The central processing unit (CPU) is therefore the device that controls the entire computer system while exchanging information with the computer's components, and since every operation of the computer is under the control of the central processing unit (CPU), it can be called the brain of the computer. Actual CPU chips often integrate not only the execution part but also additional units such as caches.

Category

Cache memory

Cache memory is general-purpose memory used to reduce the bottleneck caused by the speed difference between a fast device and a slow device. The term is widely used for devices other than the CPU as well; in a CPU, it eases the bottleneck caused by the speed difference between the CPU core (fast) and memory (slow compared to the CPU).

The L1 cache is usually built into the CPU chip and is the first to be used for data use/reference. The L1 cache typically has a capacity of about 8–64KB and is accessed fastest by the CPU; if the data is not found here, the lookup moves on to the L2 cache memory.

L2 cache memory has a similar purpose and role to the L1 cache, but it is slower. Typically about 64Kb–4MB is used. It varies slightly by CPU product, but the L2 cache is generally built onto the CPU die (circuit board) as a separate chip. As mentioned above, the L1 cache is searched first, and if the data is not there, the L2 cache is searched. Again, the L2 cache is slower than the L1 cache but faster than regular memory (RAM).

L3 cache memory works on the same principle. However, most processors these days do not have L3 cache memory, because the L2 cache covers enough. For example, the Intel Core 2 Duo and Quad have no L3 cache, while the Core i7 has 8MB. Having it is certainly better than not having it, but since only the L1/L2 cache memory directly affects CPU performance, the general trend is not to pay much attention to the L3 cache. For reference, this L3 cache is more often built into the motherboard rather than the CPU.

CPU INFO in the Linux

Ways to check CPU information on Linux are as follows.

$ cat /proc/cpuinfo
$ lscpu
$ hardinfo
$ sudo lshw -class processor
$ nproc
$ sudo dmidecode -t 4
$ cpuid ## apt-get install cpuid
$ inxi -C ## apt-get install inxi

Checking CPU temperature

See lm-sensors.

talkingaboutme.tistory.com Architecture

Study and Architecture posts in chronological order.

  • 01 - [Study] Pipeline
  • 02 - [Study] Pipeline Hazard
  • 03 - [Study] Memory Hierarchy (1)
  • 04 - [Study] Memory Hierarchy (2) - Direct Mapped Cache
  • 05 - [Study] Memory Hierarchy (3) - Cache Write Policy
  • 06 - [Study] Memory Hierarchy (4) - Sequence of Cache Write
  • 07 - [Study] Dynamic Branch Prediction
  • 08 - [Study] Single Cycle Implementation - Arithmetic Instruction
  • 09 - [Study] Single Cycle Implementation - Memory Access Instruction
  • 10 - [Study] Multi Cycle Implementation
  • 11 - [Study] Pipelined Implementation Example
  • 12 - [Computer Architecture] What is ILP?
  • 13 - [Computer Architecture] Memory Technology
  • 14 - [Computer Architecture] Motivation for Caches
  • 15 - [Computer Architecture] Classifying Caches
  • 16 - [Computer Architecture] SuperScalar Processor
  • 17 - [Distributed System] lock
  • 18 - [Distributed System] TestAndSet Lock
  • 19 - [Architecture] Memory Hierarachy
  • 20 - [Architecture] Basic of Virtual Memory (1)
  • 21 - [Architecture] Basics of Virtual Memory (2)
  • 22 - [Architecture] Page faults
  • 23 - [Architecture] Building the MMU (1)
  • 24 - [Architecture] Building the MMU (2)
  • 25 - [Architecture] Contexts
  • 26 - [Architecture] MMU improvements
  • 27 - [Architecture] Processes
  • 28 - [ARM] Registers on the ARM Cortex M4

Modern CPU architecture in 45 minutes

Intel has posted a two-part video series on YouTube that briefly covers the various elements and concepts of modern CPU architecture. (In English) The two parts together run about 45 minutes, roughly the level of an orientation for a major course taken by computer science undergraduates.

Part 1

Part 1 covers the following.

  • What is a CPU?
  • A brief history of the CPU (focused on Intel)
  • Abstraction layers of a computer
  • The concept of an ISA (instruction set architecture)

Part 2

Part 2 covers the following. It is about microarchitecture, the implementation of an ISA, and goes a bit deeper than Part 1.

  • The concept of microarchitecture
  • The four-stage instruction cycle [Fetch ▶ Decode ▶ Execute ▶ Write-back] and the front-end/back-end split in a CPU
  • Pipelines and CPU clock speed
  • Speculative execution through branch prediction
  • Caches for reducing the speed gap with memory
  • The concept of μops (Micro-operations) used inside the CPU
  • Implementing ILP (instruction-level parallelism) through superscalar execution
  • Out-of-Order Execution and the various components for implementing it
  • How a modern CPU works by combining all of these elements

CPU technology

CPU Technology (list)

Architecture

Von Neumann, Harvard (Modified Harvard), Dataflow, TTA

Instruction set

ASIP, CISC, RISC, EDGE, EPIC, MISC, OISC, VLIW, NISC, ZISC, TRIPS, Comparison

Word size

1-bit, 4-bit, 8-bit, 9-bit, 10-bit, 12-bit, 15-bit, 16-bit, 18-bit, 22-bit, 24-bit, 25-bit, 26-bit, 27-bit, 31-bit, 32-bit, 33-bit, 34-bit, 36-bit, 39-bit, 40-bit, 48-bit, 50-bit, 60-bit, 64-bit, 128-bit, 256-bit, 512-bit, variable

Execution

Instruction pipelining (Bubble * Operand forwarding), Out-of-order execution (Register renaming), Speculative execution (Branch predictor * Memory dependence prediction), Hazards

Parallel level

Bit (Bit-serial * Word), Instruction (Scalar * Superscalar), Task (Thread * Process), Data (Vector), Memory

Multithreading

Temporal, Simultaneous, Preemptive, Cooperative

Flynn's taxonomy

SISD, SIMD, MISD, MIMD (SPMD), Addressing mode

Types

Digital signal processor (DSP), GPGPU, Microcontroller (MCU), Physics processing unit, System on a chip (SoC), Cellular

Components

Address generation unit (AGU), Arithmetic logic unit (ALU), Barrel shifter, Floating-point unit (FPU), Back-side bus (Multiplexer * Demultiplexer), Registers, Memory management unit (MMU), Translation lookaside buffer (TLB), Cache, Register file, Microcode, Control unit, Clock rate

Power management

APM, ACPI, Dynamic frequency scaling, Dynamic voltage scaling, Clock gating

CPU hardware security

NX bit, Hardware restriction (firmware), Trusted Execution Technology, Secure cryptoprocessor, Hardware security module, Hengzhi chip

Favorite site

References


  1. File: ↩

  2. Configuration_of_the_computer.pdf ↩

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