ARM
lastmod 2024-12-11created 2016-11-034 edits
Glossary for newcomers to the Arm ecosystem
If you're new to the Arm ecosystem, consider this a quick primer on terms you've likely seen before but might have questions about.
The Arm architecture is a family of RISC (reduced instruction set computer) architectures that use simple addressing modes. Data processing is done on register operands, relying on loads and stores to move data into and out of registers.
- The Arm architecture is a RISC family with simple addressing modes
- Arm Limited is the British company that manages the Arm architecture
- ARM went from Acorn RISC Machine to Advanced RISC Machines
- The Arm ARM (Architecture Referecnce Manual) is the programming manual for Arm
- Armv9 is the latest in the architecture family (at the time of writing). Adds SIMD vectors (SVE), matrix operations (SME/SME2), and more
- Armv9.4-A is the latest batch of extensions to Armv9. These extensions are documented in the Arm ARM. Some extensions are optional when introduced but are planned to become mandatory in future versions
- The A in Armv9.4-A stands for "Application Profile". It supports virtual memory through an MMU and is seen in all Arm systems such as phones/laptops/servers.
- There are also others, such as "R" for real-time systems and "M" for microcontrollers without an MMU.
- These three architecture profiles are, again, "A" "R" "M"
- AArch64 is an "execution state" introduced in ARMv8. Supports 64b registers (31 general-purpose registers, a dedicated 64b stack pointer, a 64b program counter, a zero-value pseudo register)
- Along with this, the 32b functionality used in ARMv7 was named AArch32
- Interestingly, the Arm ARM does not mention the term ARM64 (Apple, Microsoft, and Linus Torvalds prefer it)
- The name ultimately makes sense; the arm64 Linux kernel can run user space code in the AArch64 or AArch32 execution state, but the kernel itself is AArch64-only
- A64 is the instruction set introduced with AArch64. In practice, it is the only instruction set AArch64 supports. AArch64 registers are 64b, but the instructions themselves are still 32b (fixed width)
- A32 refers to the older ISA. It is also 32b fixed width. T32 is the instruction set used before Armv8 and refers to 32b and 16b Thumb2
- Not to be confused with A64 is "A78" used to refer to a core; this is the Cortex-A78.
- Arm designs not only the Arm architecture but also implementations of the architecture, which we call microarchitectures. If you see the word Cortex or Neoverse, regardless of the number that follows, these are microarchitectures designed by Arm.
- For example, the Cortex-A78 implements extensions up to ArmV8.3. Wikipedia has a template summarizing this
- DynamIQ (formerly bit.LITTLE) is based on the idea of using heterogeneous rather than homogeneous cores in a multicore system
- The advantage of this design is that different cores can be good at different things at different times. Power-hungry Out-of-order processors are used when performance is needed, and slower in-order cores are used to reduce power consumption
- It's interesting to see Intel doing similar work with performance/efficiency cores in Alder Lake
- Digging through the reference manuals, the various Execution States have evolved in interesting ways: A55, X1, X3, etc.
- Legacy terms
- ARM9 should not be confused with Armv9. It is a family of cores, some of which implement ARMv4t and some ARMv5
- StrongARM is a series of ARMv4 CPUs made by DEC. Intel acquired this IP through a lawsuit settlement and eventually designed its own ARMv5 microarchitecture called XScale
- Eventually Intel sold the PXA SoC family that used XScale to Marvell. One wonders what the world would look like if Intel had stuck with XScale alongside/instead of Atom
- ARMv4 introduced a compressed instruction set called Thumb. Its instructions are 16b fixed width
- ARMv6t2 introduced Thumb2. Supports 32b instructions, UAL (Unified Assembly Language), and more
ARM Cortex-M3
See also
- gARM - High-performance Go compiler specialized for ARM64